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RT9045 1 ds9045-04 august 2011 www.richtek.com cost-effective, 1.8a sink/source bus termination regulator ordering information general description the RT9045 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system to comply with the devices requirements. the regulator is capable of actively sinking or sourcing up to 1.8a while regulating an output voltage to within 20mv. the output termination voltage can be tightly regulated to track v ddq / 2 by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the refen pin voltage. the RT9045 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shutdown protection. features z z z z z ideal for ddr v tt applications z z z z z sink and source current : ddrii 1.8a sink/source @ v in = 1.8v ddriii 1.5a sink/source @ v in = 1.5v lpddriii 1.2a sink/source @ v in = 1.35v ddriv 1.2a sink/source @ v in = 1.2v z z z z z integrated power mosfets z z z z z generate termination voltage for ddr memory interfaces z z z z z stable with output ceramic capacitor z z z z z high accuracy output voltage at full-load z z z z z output adjustment by two external resistors z z z z z low external component count z z z z z shutdown for suspend to ram (str) functionality with high impedance output z z z z z current limiting protection z z z z z on-chip thermal protection z z z z z rohs compliant applications z desktop pcs, notebooks, and workstations z graphics card memory termination z set top boxes, digital tvs, printers z embedded systems z active termination buses z ddr memory systems note : richtek products are : rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. suitable for use in snpb or pb-free soldering processes. pin configurations (top view) sop-8 (exposed pad) vin gnd refen vout nc nc nc vcntl gnd 2 3 4 5 6 7 8 9 marking information RT9045 gspymdnn RT9045gsp : product number ymdnn : date code package type sp : sop-8 (exposed pad-option 2) RT9045 lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) RT9045 zspymdnn RT9045zsp : product number ymdnn : date code RT9045gsp RT9045zsp free datasheet http:///
RT9045 2 ds9045-04 august 2011 www.richtek.com typical application circuit test circuit figure 1. output voltage tolerance, v load figure 2. current in shutdown mode, i stby r 1 = r 2 = 100k , r tt = 50 / 33 / 25 r dummy = 1k as for v out discharge when v in is not presented but v cntl is presented c out = 10 f (ceramic) under the worst case testing condition c in = 10 f, c cntl = 1 f, c ss = 1nf to 0.1 f vin refen gnd vcntl vout RT9045 0.9v/0.75v/0.675v/0.6v c out i l v out v v in = 1.8v/1.5v/1.35v/1.2v v cntl = 5v vin refen gnd vcntl vout RT9045 v in = 1.8v/1.5v/1.35v/1.2v 0.9v/0.75v/0.675v/0.6v c out v out v r l 0.9v 0v r l and c out time delay 0.15v a v cntl = 5v vin refen gnd vcntl vout RT9045 r1 r2 c ss v in = 1.8v/1.5v/1.35v/1.2v v cntl = 5v c cntl c in r tt c out r dummy en 2n7002 r3 2.2 free datasheet http:///
RT9045 3 ds9045-04 august 2011 www.richtek.com figure 3. current limit for high side, i lim figure 4. current limit for low side, i lim figure 5. refen pin shutdown threshold, v ih & v il vin refen gnd vcntl vout RT9045 0.9v/0.75v/0.675v/0.6v c out i l v out v v in = 1.8v/1.5v/1.35v/1.2v v cntl = 5v a vin refen gnd vcntl vout RT9045 v in = 1.8v1.5v/1.35v/1.2v 0.9v/0.75v/0.675v/0.6v c out i l v out v a power supply with current limit v cntl = 5v vin refen gnd vcntl vout RT9045 v in = 1.8v/1.5v/1.35v/1.2v c out v out v r l 0.9v/0.75v 0v r l and c out time delay 0.9v/0.75v/0.675v/0.6v 0.15v v out v refen v out would be low if v refen < 0.15v v out would be high if v refen > 0.4v v cntl = 5v free datasheet http:///
RT9045 4 ds9045-04 august 2011 www.richtek.com functional pin description vin input voltage which supplies current to the output pin. connect this pin to a well-decoupled supply voltage. to prevent the input rail from dropping during large load transient, a large, low esr capacitor is recommended to use. the capacitor should be placed as close as possible to the vin pin. gnd (exposed pad) common ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. vcntl vcntl supplies the internal control circuitry and provides the drive voltage. the driving capability of output current is proportioned to the vcntl. connect this pin to 5v bias supply to handle large output current with at lea st 1 f capacitor from this pin to gnd. an important note is that vin should be kept lower or equal to vcntl. function block diagram gnd vcntl refen current limit thermal protection + - ea vout vin refen reference voltage input and active low shutdown control pin. two resistors dividing down the vin voltage on this pin to create the regulated output voltage. pulling this pin to ground turns off the device by an open-drain, such as 2n7002, signal n-mosfet. vout regulator output. vout is regulated to refen voltage that is used to terminate the bus resistors. it is capable of sinking and sourcing current while regulating the output rail. to maintain adequate large signal transient response, typical value of 10 f ceramic capacitors are recommended to reduce the effects of current transients on vout. free datasheet http:///
RT9045 5 ds9045-04 august 2011 www.richtek.com electrical characteristics (v in = 1.8v / 1.5v, v cntl = 5v, v refen = 0.9v / 0.75v, c out = 10 f (ceramic), t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit input vcntl operation current i cntl i out = 0a -- 0.7 2.5 ma vcntl power on reset v por v cntl rising -- 3.6 -- v standby current (note 5) i stby v refen < 0.2v (shutdown), r load = 180 -- 20 90 a output output offset voltage (note 6) v os i out = 0a ? 13 -- 13 mv v in = 1.8v, v refen = 0.9v, i out = 1.8a v in = 1.5v, v refen = 0.75v, i out = 1.5a v in = 1.35v, v refen = 0.675v, i ou t = 1.2a load regulation (note 7) v load v in = 1.2v, v refen = 0.6v, i out = 1.2a ? 13 -- 13 mv protection v in = 1.8v, v refen = 0.9v source i limitsr v in = 1.5v, v refen = 0.75v 1.8 -- 3.5 a v in = 1.8v, v refen = 0.9v current limit sink i limitsk v in = 1.5v, v refen = 0.75v 1.8 -- 3.5 a absolute maximum ratings (note 1) z input voltage, v in ------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v z control voltage, v cntl ----------------------------------------------------------------------------------------------------- ? 0.3v to 6v z reference input voltage, v refen ----------------------------------------------------------------------------------------- ? 0.3v to 6v z output voltage, v out ------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) ----------------------------------------------------------------------------------------------------- 1.163w z package thermal resistance (note 2) sop-8 (exposed pad), ja ------------------------------------------------------------------------------------------------ 86 c /w sop-8 (exposed pad), jc ----------------------------------------------------------------------------------------------- 15 c /w z junction temperature ------------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z input voltage, v in ------------------------------------------------------------------------------------------------------------ 1v to 5.5v z control voltage, v cntl ----------------------------------------------------------------------------------------------------- 5v 5% z junction temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 85 c to be continued free datasheet http:///
RT9045 6 ds9045-04 august 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the exposed pad for package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on refen pin (v il < 0.15v). it is measured with v in = 1.8v, v cntl = 5v. note 6. v os offset is the voltage measurement defined as v out subtracted from v refen . note 7. regulation is measur ed at constant junction temperature by using a 5ms current pulse. devices are tested for load regulation in the load range from 0a to 1.8a peak. parameter symbol test conditions min typ max unit short circuit current v in = 1.8v / 1.5v / 1.35v / 1.2v, v out < 0.2v -- 1.5 -- a thermal shutdown temperature t sd v cntl = 5v 125 170 -- c thermal shutdown hysteresis t sd v cntl = 5v -- 35 -- c short circuit current v in = 1.8v / 1.5v / 1.35v / 1.2v, v out < 0.2v -- 1.5 -- a thermal shutdown temperature t sd v cntl = 5v 125 170 -- c thermal shutdown hysteresis t sd v cntl = 5v -- 35 -- c refen shutdown v ih enable 0.4 -- -- shutdown threshold v il shutdown -- -- 0.15 v free datasheet http:///
RT9045 7 ds9045-04 august 2011 www.richtek.com typical operating characteristics low-v ddr iii output voltage vs. temperature 0.596 0.597 0.598 0.599 0.600 -50-25 0 25 50 75100125 temperature (c) output voltage (v) v in = 1.2v, v refen = 0.6v, v cntl = 5v, i out = 0a refen threshold voltage vs. temperature 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 temperature (c) refen threshold voltage (v) 1 v cntl = 5v, i out = 0a rising falling ddr ii output voltage vs. temperature 0.898 0.899 0.900 0.901 0.902 0.903 0.904 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 1.8v, v refen = 0.9v, v cntl = 5v, i out = 0a ddr iii output voltage v s. temperature 0.748 0.749 0.750 0.751 0.752 0.753 0.754 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 1.5v, v refen = 0.75v, v cntl = 5v, i out = 0a vcntl current vs. temperature 0.5 0.6 0.6 0.7 0.7 0.8 0.8 -50 -25 0 25 50 75 100 125 temperature (c) vcntl current (ma) ddr ii ddr iii v cntl = 5v, i out = 0a low-v ddr iii source current limit vs. temperature 1.6 1.8 2.0 2.2 2.4 2.6 -50 -25 0 25 50 75 100 125 temperature (c) source current limit (a) ddr ii ddr iii free datasheet http:///
RT9045 8 ds9045-04 august 2011 www.richtek.com time (250 s/div) 0.9v tt @ 1.8a transient response output voltage (mv) 20 0 -20 output current (a) 2 1 0 -1 -2 v in = 1.8v, v ref/en = 0.9v, v cntl = 5v time (250 s/div) 0.6v tt @ 1.2a transient response output voltage (mv) 20 0 -20 output current (a) 2 1 0 -1 -2 v in = 1.2v, v ref/en = 0.6v, v cntl = 5v time (250 s/div) 0.75v tt @ 1.5a transient response output voltage (mv) 20 0 -20 output current (a) 2 1 0 -1 -2 v in = 1.5v, v ref/en = 0.75v, v cntl = 5v sink current limit vs. temperature 1.6 1.8 2.0 2.2 2.4 2.6 -50-250 255075100125 temperature (c) sink current limit (a ) ddr ii ddr iii free datasheet http:///
RT9045 9 ds9045-04 august 2011 www.richtek.com application information output voltage setting the RT9045 is a high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system. besides, the RT9045 could also serves as a general linear regulator. the RT9045 accepts an external reference voltage at the refen pin and provides an output voltage regulated to this reference voltage level as shown in figure 6, where v out = v in x r2 / (r1 + r2) shutdown control refer to the ? typical application circuit ? . make sure the current sinking capability of pull-down n-mosfet is enough for the chosen voltage divider to pull-down the voltage at refen pin below 0.15v to shutdown the device. in addition, the capacitor c ss and voltage divider form the low-pass filter. soft-start the RT9045 builds in an internal soft-start circuit to prevent inrush current during start-up. the internal soft-start time depends on refen voltage. for ddriii application (refen = 0.75v), soft-start time is around 100 s. current limit & short circuit protection the RT9045 implements the current limit and output short protection circuit against the unexpected applications. the current limit circuit monitors and controls the pass transistor's gate voltage, providing the load current up to at least 1.8a. if the load current exceeds the current limit trip point, RT9045 will soon reduce the load current to around 1.5a constantly, refer to figure 8. if the output voltage is abruptly pulled down to less than 0.2v, the short circuit protection is triggered and then maintains the load current at 1.5a. it prevents RT9045 from being damaged in case an output short to ground event occurs. general regulator like other linear regulator, dropout voltage and thermal issue should be specially considered. figure 7 shows the r ds(on) vs. temperature curve of RT9045. the minimum dropout voltage could be obtained by the product of r ds(on) and output current. for thermal consideration, please refer to the relative section. figure 7. r ds(on) vs. temperature figure 8. output voltage vs. output current output voltage vs. output current 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 output current (a) output voltage (v) ddr ii ddr iii v cntl = 5v low - v ddr iii figure 6. RT9045 operating as a linear regulator r ds(on) vs. temperature 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -50 -25 0 25 50 75 100 125 temperature (c) r ds(on) ( ? ) v cntl = 5v vin refen gnd vcntl vout RT9045 v refen r1 r2 5v v out v in free datasheet http:///
RT9045 10 ds9045-04 august 2011 www.richtek.com 0 10 20 30 40 50 60 70 80 90 100 0 1020304050607080 copper area (mm 2 ) thermal resistance ja (c/w) figure 11. relation between thermal resistance ja and copper area figure 9. sop-8 (exposed pad) package sectional drawing ambient molding compound gold line lead frame die pad case (exposed pad) pcb figure 10. thermal re sistance equivalent circuit junction r die r die-attach r die-pad r gold-line r lead frame case (exposed pad) r pcb r pcb ambient r molding-compound path 1 path 2 path 3 thermal consideration RT9045 regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. for continued operation, do not exceed absolute maximum operation junction temperature of 125 c. the power dissipation definition in device is : p d = (v in ? v out ) x i out + v in x i q the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. the junction to ambient thermal resistance for sop-8 (exposed pad) package is 86 c/w on the standard jedec 51-7 (4 layers, 2s2p) thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (86 c/w) = 1.163w figure 9 shows the package sectional drawing of sop-8 (exposed pad). every package has several thermal dissipation paths. as shown in figure 10, the thermal resistance equivalent circuit of sop-8 (exposed pad). the path 2 is the main path due to these materials thermal conductivity. we define the exposed pad is the case point of the path 2. the thermal resistance ja of sop-8 (exposed pad) is determined by the package design and the pcb design. however, the package design has been decided. if possible, it ' s useful to increase thermal performance by the pcb design. the thermal resistance can be decreased by adding copper under the sop-8 (exposed pad) package. input capacitor and layout consideration place the input bypass capacitor as close as possible to the RT9045. a low esr capacitor larger than 20 f is recommended for the input capacitor. use short and wide traces to minimize parasitic resistance and inductance. inappropriate layout may result in large parasitic inductance and cause undesired oscillation between the RT9045 and the proceeding power converter. figure 11 shows the relation between thermal resistance ja and copper area on a standard jedec 51-7 (4 layers, 2s2p) thermal test board at t a = 25 c. we have to consider the copper couldn ' t stretch infinitely and avoid the tin overflow. we use the ? dog-bone ? copper patterns on the top layer as shown in figure 12. free datasheet http:///
RT9045 11 ds9045-04 august 2011 www.richtek.com as shown in figure 13, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad of 2 oz. copper (figure 13.a), ja is 86 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 13.b) reduces the ja to 73 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 13.d) reduces the ja to 65 c/w. figure 12. dog-bone layout exposed pad w Q 2.28mm figure 13. thermal resistance vs. copper area layout thermal design (a) copper area = 10mm 2 , ja = 86 c/w (b) copper area = 30mm 2 , ja = 73 c/w (c) copper area = 50mm 2 , ja = 68 c/w (d) copper area = 70mm 2 , ja = 65 c/w free datasheet http:///
RT9045 12 ds9045-04 august 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.700 5.100 0.185 0.200 b 3.800 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.790 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.513 0.083 0.099 option 2 y 3.000 3.500 0.118 0.138 outline dimension free datasheet http:///

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